The processes by which integrated circuit are fabricated are extremely complex. For the present purposes, integrated circuits include devices such as those formed on monolithic semiconducting substrates, such as group IV materials like silicon or germanium or mixtures of such, or group III-V compounds such as gallium arsenide. Because the processes are so complex, there are an extreme number of variables that can effect the final outcome of a process, even when measured against a criterion as generalized as “pass” or “fail.”
For this reason, engineers attempt to limit the variability of as many processing parameters as possible, and then attempt to strictly monitor and control the dramatically fewer in number parameters which may need to be modified from time to time. Typically, the various dependent parameters that change in value with a given process are carefully monitored, and may even be charted, such as on a statistical process control chart, so that the engineer can more readily determine whether one or more of the myriad independent parameters on which the process depends has shifted or otherwise gone out of control.
Semiconductor manufactures make integrated circuits by placing repeated patterns of devices on the substrates. The patterned devices are typically rectangular, and are generally disposed in a rectilinear array on a circular substrate. How the device array is placed on the substrate tends to effect the number of whole devices that can fit on the substrate, which in turn effects the total possible number of devices that can be obtained from that substrate. Thus, obtaining a maximum number of whole devices on a substrate is one consideration in deciding how to place the device array on the substrate. However, there are often other things to be considered when deciding how to place the device array on the substrate, such as the number of exposure fields that are required to produce the device array, which in turn effects lithography cell throughput, and what portions of the substrate tend to produce a higher yield or other properties than other portions, which also effects the total device yield of the substrate.
There are at least two problems inherent in the process described above. The first problem is to determine the placement of the devices so as to optimize a given integrated circuit property. The second problem is to determine an overall optimum layout that considers the tradeoffs between the various competing properties that may be dependent on the layout of the devices, but which typically do not have the same optimum layout.
What is needed, therefore, is a system for calculating and displaying an optimum device layout when multiple optimization factors are considered.